The present invention relates to semiconductor integrated circuits and more specifically to methods and apparatus for blowing and sensing antifuses.
To increase device yield, semiconductor integrated circuits such as DRAM and SRAM memories employ redundant circuitry that allows the integrated circuits to function despite the presence of one or more manufacturing or other defects (e.g., by employing the redundant circuitry rather than the original, defective circuitry). For example, conventional DRAM and SRAM memories often use laser fuse blow techniques as part of their redundancy scheme wherein redundant circuitry may be employed in place of defective circuitry by blowing one or more fuses with a laser beam.
While laser fuse blow techniques improve device yield, several problems remain. Laser fuse blow techniques must be performed at the wafer level and thus are time consuming and costly. For example, a wafer typically must leave a test station for fuses to be blown, and then return to the test station for verification. For DRAM memories, post burn-in module fallout may range from 25% or higher for early hardware in a new technology to less than 5% as the technology matures. Of these post burn-in module fallouts, approximately 80% are due to single cell bit failures. While single cell fails are recoverable with redundancy, laser fuse blow techniques cannot be applied to modules. Device yield therefore remains low despite the use of laser fuse blow techniques. Accordingly, a need exists for improved techniques for implementing redundancy within semiconductor integrated circuits.
As described in previously incorporated U.S. patent application Ser. No. 09/466,495, filed on even date herewith (titled xe2x80x9cANTIFUSES AND METHODS FOR FORMING THE SAMExe2x80x9d), electronically programmable antifuses may be advantageously employed in place of laser blown fuses in redundant circuit applications because antifuses are blowable at the module level of a circuit design (while a wafer remains at a test station), as well as at the wafer level. However, to implement antifuse based redundancy schemes, it must be possible to sense the state of antifuses (e.g., whether or not an antifuse is blown so as to identify which array bits are bad and should be replaced), to blow antifuses (e.g., to actually implement redundant circuitry) and to generate the relatively high voltages required to blow antifuses (e.g., about 5 to 9 volts or higher). The present invention provides methods and apparatus for performing each of these functions.
In a first aspect of the invention, a method is provided for changing the state of one of a plurality of antifuses. The method includes selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse (e.g., to blow the selected antifuse).
In a second aspect of the invention, an apparatus is provided for changing the state of one of a plurality of antifuses each having a first and a second terminal. The apparatus includes a write/sense line and a plurality of selection devices. Each selection device is connected to the write/sense line, is adapted to connect to the second terminal of a different one of the plurality of antifuses and is adapted to select an antifuse by connecting the antifuse""s second terminal to the write/sense line in response to a selection signal. The apparatus also includes a high voltage signal line adapted to connect to the first terminal of each of the plurality of antifuses and to apply a high voltage thereto that changes the state of any selected antifuse.
In a third aspect of the invention, an apparatus is provided for changing the state of an antifuse having a first and a second terminal. The apparatus includes a first voltage terminal and a selection device adapted to connect to the second terminal of the antifuse and connected to the first voltage terminal. The selection device is further adapted to select the antifuse by connecting the antifuse""s second terminal to the first voltage terminal in response to a selection signal. The apparatus also includes a high voltage signal line adapted to connect to the first terminal of the antifuse and to apply a high voltage thereto that changes the state of the antifuse when the antifuse is selected.
In a fourth aspect of the invention, a method is provided for boosting a voltage (e.g., to a voltage sufficient to blow an antifuse). The method includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling approximately twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating approximately thrice the first voltage based on the second voltage of the second stage voltage booster circuit.
In a fifth aspect of the invention, a voltage booster circuit is provided. The voltage booster circuit includes a first stage voltage booster circuit having a first, first stage storage mechanism adapted to store a first voltage and a second stage voltage booster circuit connected to the first stage voltage booster circuit and having a first, second stage storage mechanism and a second, second stage storage mechanism each adapted to store approximately the first voltage. A first transfer mechanism is connected between the first and second voltage booster circuits and is adapted to transfer approximately twice the first voltage from the first stage voltage booster circuit to the second stage voltage booster circuit. A second transfer mechanism is connected to the second stage voltage booster circuit and is adapted to transfer approximately thrice the first voltage from the second stage voltage booster circuit.
The first, second and third aspects of the invention allow the state of an antifuse to be sensed and changed, while the fourth and fifth aspects of the invention allow the relatively high voltages required to blow an antifuse to be generated, preferably on-chip without requiring external connections.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiments, the appended claims and the accompanying drawings.